Technological advances in computer components are providing continually refined microprocessors, memories and support chips for modern personal computer systems. The inevitable evolution of the memory systems coupled to these computer systems have allowed system designers flexibility to tune them for maximum performance at a reasonable cost. This evolution is evident in the memory types currently available for personal computers. Non-parity memory, which offers no error checking when data is read from memory, has historically been installed in lower cost computer systems. Parity memory, which provides the ability to check data read from memory against parity bits to determine if any data stored in memory is incorrect, has been reserved for commercial customers requiring data integrity and high performance. The computer systems of commercial customers have also been the prevalent users of memories having error checking and correcting capability (ECC) which allows the detection and correction of certain memory errors. Memory systems with ECC capability have typically had a higher cost and lower performance then comparable parity systems. The evolution in computer memories have resulted in closure of the gap between the cost of memories having parity and ECC, and system designers are now faced with providing the appropriate memory choice for its users.
One prior art technique provides either parity or ECC capability in a large scale integration (LSI) chip. The LSI chip provides error detection and correction circuits which operates in a modified Hamming code, so that each error detection and correction circuit may generate either ECC parity bits for single error correction and double error detection, or generate byte parity bits for byte error detection. The chosen code permits the generation of syndrome bits for correcting single bit errors, with the same group of syndrome bits delivered to each of plural data "sliced" data chips when correcting the bit in error, so that each of the data chips may be constructed identically. While the technique delivers either capability, the implementation requires complex LSI components which must be customized to a particular implementation. In addition, the technique provides no ability to allow the user to easily switch between parity or non-parity capability to increase the performance of a computer system.
Another prior art technique discloses a personal computer having enhanced memory access capabilities where ECC and parity error checking can be selectively chosen for memory elements installed in the computer system. The technique discloses non-adjacent placement of the necessary bits for error detection from the data bits. Dynamic random access memory (DRAM) cards are arranged in sockets. The presence or absence of DRAM cards in particular sockets allows a user to switch between ECC and parity operation. The technique provides a low cost method of using the same memory cards in a computer system to select either ECC or parity operation. The technique suffer from a requirement of arranging the cards in the particular sockets to obtain the preferred operation. In addition, certain sockets must be left empty within the computer system resulting in loss of space or increased computer size.
Consequently, it would be desirable to provide a technique for providing either parity or ECC memory that is easily selectable by a user in a computer system.